## SystemVerilog Studio tools

This project's SystemVerilog/Verilog/UVM code is open in a JetBrains IDE with SystemVerilog Studio, connected over
MCP (the `jetbrains` server). Its `sv_` tools answer from the IDE's understanding of the code (scopes, packages,
includes, macros, the compile file), which grep and reading files cannot. Use them as follows.

- **Start** with `sv_project_info()`: the compile file and defines in use. If it reports problems (a package or an
  include not found, UVM not in the project), tell the user: results in those files are incomplete.
- **No compile file** (`sv_project_info` says `compile_file_chosen: "none"`, or several `.f` files and none
  chosen): make one from the top with `sv_create_compile_file(top=…)` — read the dry run (`ambiguous`: pass
  `prefer=[dirs]`; `unresolved`; `binds_available`), then `apply=true`; slang, the hierarchy and the run
  configurations use it.
- **Find a declaration** with `sv_find_symbol(name=…)`, not grep. **Before changing a declaration**, list its uses
  with `sv_find_references(file=…, line=…, column=…)`; read its `inactive` list too (uses in `ifdef code that is
  not compiled now).
- **Before writing an instance or a call**, get the interface with `sv_module_interface(name=…)`: ports in order
  with direction and width, parameters with defaults; `inactive_ports` / `inactive_parameters` exist in other
  builds (connect them inside the same `ifdef if needed).
- **Before writing a sequence, test or scoreboard**, get the class's members with `sv_members(name=…)` (with
  `file=…` when the name has several definitions).
- **Macros**: see what a call expands to with `sv_expand_macro(call=…)` or at a place; read its `conditions`.
- **Hierarchy**: who instantiates a module and what it instantiates, with `sv_instances(name=…)`.
- **Elaborated hierarchy** (parameter values as elaborated, generate loops unrolled; needs slang-server, see
  `sv_project_info` `toolchain`): `sv_hierarchy(path="", depth=…)`, `sv_hierarchy(module=…)` for its instances,
  `sv_hierarchy(search=…)` to find a name anywhere, `sv_hierarchy(list="modules")` for instance counts.
- **Run lint or a simulation** (when the user allowed it in Settings | Languages & Frameworks | SystemVerilog | Coding
  Agents): `sv_run(configuration=…)` — parsed problems, `passed`, UVM counts, the log; prefer it to
  `execute_run_configuration` for SystemVerilog tools.
- **Read a file's structure, not its text**: `sv_outline(file=…)` — units, ports, signals, instances, blocks and what
  they assign, subroutines, with lines; read only the lines you need afterwards.
- **Apply a quick fix** sv_check lists (Connect missing ports, Change to 'name', Import pkg::*): `sv_apply_fix(file=…,
  line=…, column=…, fix=…)` — a dry-run diff first, then `apply=true`; do not write the fix by hand. It works on written files (after a
  `content` check, write the file first).
- **Elaborated connectivity** (by hierarchical path, through ports, per instance; needs slang-server):
  `sv_elaborated_drivers(path=…, loads=…, depth=…)`; for statement-precise drivers at a source line use `sv_drivers`.
- **Who drives a signal, where does it go**: `sv_drivers(file=…, line=…, column=…)` at its declaration or a use
  (`loads=true` for its readers; `depth` follows output ports into children and input ports up to parents), instead of
  grepping for assignments.
- **Check before you write**: run `sv_check(files=[…], content=…)` with the full text you intend to write to that
  existing file (one file; for a new file, write it, then check); fix what it reports, then write. **After writing**,
  run `sv_check(files=[…])` on the files you changed and the files that use what you changed.
  `unresolved` means some checks were skipped: no problems is not a pass then. It is not a simulator or linter.
- **Rename** with `sv_rename(…)`, never search-and-replace: read the dry-run diff, `conflicts` and `notes` (what it
  does not rename: inactive code, unresolved paths), then `sv_rename(apply=true)`.
- **verilog-mode AUTOs** (`/*AUTOINST*/`, `/*AUTOARG*/`, …): expand with `sv_expand_autos(files=[…])`, read the
  diff, then `sv_expand_autos(apply=true)`; do not write AUTO output by hand.
- Paths are project-relative. When a result says `timed_out` or `more`, ask again with a longer `timeout` or the
  next `offset`.