Skip to content
SystemVerilog Studio

SystemVerilog Studio

SystemVerilog and UVM support for IntelliJ IDEA, CLion, PyCharm and other JetBrains IDEs.
Get startedDownload the sample project
What the video shows
  1. top.sv instantiates the module counter.
  2. Go to Declaration (⌘B / Ctrl+B) opens its definition in counter.sv.
  3. Find Usages (⌥F7 / Alt+F7) lists every usage, including the end label endmodule : counter.
  4. Names are colored by what they are (shown in the SystemVerilog Studio Dark color scheme).

Navigate

Jump from any name to its declaration — modules, interfaces, packages, classes, ports, parameters, signals, enum members, generate blocks — across files and through obj.member chains. Go to Declaration

Find usages

See every place a declaration is used, including end labels, named connections, imports, pkg:: and Class:: references and hierarchical paths. Find Usages

Rename safely

Rename updates every usage, keeps related declarations together (virtual method overrides, Verilog-95 output q; reg q;) and warns you before a rename would change what your code means. Rename

Built for UVM

Works on real testbenches: virtual interfaces, uvm_config_db#(virtual my_if), type_id::create, parameterized sequences and drivers, clocking blocks, bind. UVM testbenches