Navigate
Jump from any name to its declaration — modules, interfaces, packages, classes, ports, parameters, signals,
enum members, generate blocks — across files and through obj.member chains.
Go to Declaration
SystemVerilog Studio
SystemVerilog and UVM support for IntelliJ IDEA, CLion, PyCharm and other JetBrains IDEs.
Find usages
See every place a declaration is used, including end labels, named connections, imports, pkg:: and
Class:: references and hierarchical paths. Find Usages
Rename safely
Rename updates every usage, keeps related declarations together (virtual method overrides, old-style Verilog
output q; reg q; pairs) and warns you before a rename would change what your code means.
Rename
Built for UVM
Works on real testbenches: virtual interfaces, uvm_config_db#(virtual my_if), type_id::create,
parameterized sequences and drivers, clocking blocks, bind. UVM testbenches
For coding agents (MCP)
Claude Code, Codex, Cursor, Junie and other agents ask the IDE through its MCP server: where a name is declared, who instantiates a module, what a macro expands to, what problems a file has, and rename safely, with a preview first. Coding agents (MCP)
More in the guide
Section titled “More in the guide”Code completion, instance and port checks, undeclared-name checks, verilog-mode AUTOs, formatting and live templates are under Editing in the sidebar; running a simulator from the IDE is under Running. SystemVerilog Studio is a paid plugin: see License.