Rename

Put the caret on a declaration or on any usage of it and choose Refactor | Rename… (⇧F6 on macOS, Shift+F6 on Windows/Linux). In the Rename dialog, type the new name and click Refactor. The declaration and every usage that Find Usages would list are updated, in all files.

Leave Search in comments and strings unchecked (the default): when it is checked, matching text in comments and string literals is replaced too.

What the video shows

1. In classes/shapes.sv, the caret is on the virtual method area of class shape; ⇧F6 (Shift+F6) opens the Rename dialog.
2. The new name get_area is entered and Refactor is clicked.
3. The overrides in square and circle and the call s.area() are renamed too.

Every declared construct can be renamed — see Supported constructs. Before changing anything, the plugin checks that the rename keeps the meaning of your code; if it would not, you get a list of conflicts first.

What is renamed together

Some declarations belong together and are always renamed as a group:

Situation	What happens
End labels	endmodule : counter, endclass : my_item, endfunction : f, end : seq follow the name.
Virtual methods	Renaming a virtual method renames the whole override family: the base declaration and every override in derived classes, plus all calls. You can start from the base method or from any override.
Verilog-95 ports	In module m(clk, q); output [7:0] q; reg [7:0] q; the port list entry, the output declaration and the reg/wire declaration are one signal and are renamed together.
Implicit port connections	.clk connects a port and a signal of the same name. Renaming either one rewrites it as an explicit connection: .clock(clk) when the port is renamed, .clk(clock) when the signal is.
Generate branches	A label or signal declared in mutually exclusive if/else generate branches is one name; renaming it renames every branch, so hierarchical references stay valid.
Duplicate definitions	If the same module or function is defined in several files (for example alternatives selected with `ifdef), usages refer to all of them, so all definitions are renamed. You are told about it first.

With the default options, text in comments and in string literals is not changed: after renaming the property vif, the configuration key in uvm_config_db#(virtual my_if)::get(this, "", "vif", vif) is still "vif".

Examples

Renaming the port clk of counter to clock

// rtl/top.sv, before
counter #(.MAX(20)) u_counter(.clk, .rst_n, .count(count), .done(done));
// after
counter #(.MAX(20)) u_counter(.clock(clk), .rst_n, .count(count), .done(done));

Renaming the Verilog-95 output q to dout — before

module legacy_reg(clk, d, q);
  output [7:0] q;
  reg [7:0] q;
  always @(posedge clk)
    q <= d;

After

module legacy_reg(clk, d, dout);
  output [7:0] dout;
  reg [7:0] dout;
  always @(posedge clk)
    dout <= d;

Limitations

• Usages inside macro definitions and macro arguments are not updated.
• Files attached as libraries are never modified. If a rename would require it — for example renaming a method that overrides a method of a library class — you get a conflict instead.
• If the base class is not available at all (for example the UVM library is not in the project), renaming a method that overrides a base-class method cannot be checked: the rename goes ahead and the method no longer overrides the base method.
• See Known limitations for the complete list.

Try it

1. In the sample project, open rtl/counter.sv, put the caret on counter in module counter, press ⇧F6 (Shift+F6), type up_counter and click Refactor. The module and its end label endmodule : up_counter change, and so does the instantiation in rtl/top.sv. Undo with ⌘Z (Ctrl+Z).
2. In rtl/counter.sv, rename the port clk to clock. @(posedge clock …) is updated, and in rtl/top.sv the implicit connection .clk becomes .clock(clk). Undo.
3. In rtl/top.sv, rename the input rst_n to reset_n. The implicit connection .rst_n becomes .rst_n(reset_n): the port of counter keeps its name. Undo.
4. Open rtl/legacy_reg.v and rename q in output [7:0] q; to dout. The port list, the output declaration, the reg declaration and the assignment all change. Undo.
5. Open classes/shapes.sv and rename area in class shape to get_area. The overrides in square and circle and the call s.area() are renamed too. Undo.
6. In rtl/top.sv, rename busy in logic busy; to active. The hierarchical reference becomes g_lane[0].active. Undo.
7. In rtl/counter_pkg.sv, rename the enum member IDLE to RESET. state <= RESET; in rtl/counter.sv is updated through the package import. Undo.