UVM testbenches

Go to Declaration, Find Usages and Rename understand the patterns UVM testbenches are built from:

Pattern	Example	What works
Virtual interfaces	virtual my_if vif; … vif.req <= 1;	The interface type, its signals through vif., clocking items through vif.cb. and modports
Configuration database	uvm_config_db#(virtual my_if)::get(this, "", "vif", vif)	The interface in the type argument and the vif handle; the string key "vif" is left alone
Factory	my_agent::type_id::create("agt", this)	The class name before ::type_id
Parameterized base classes	class my_driver extends uvm_driver #(my_item);	The class in the type argument
Component hierarchy	agt.drv.vif = null;	Each step of the member chain, across classes
Sequence items	rand bit [7:0] addr; with constraint c_addr { addr < 8'h10; }	Fields in constraints and through handles (it.addr)
Phase methods	virtual function void build_phase(uvm_phase phase);	Overrides in your classes; super.build_phase(phase) refers to the library method and is not changed
Clocking blocks and modports	clocking cb @(posedge clk); output req; endclocking	The block (vif.cb), its items (vif.cb.req), default clocking cb;, modport mp(clocking cb)
Bind	bind dut chk u_chk(.clk(clk));	The target module; port expressions resolve in the target module; the bound instance inside the target module (u_chk.flag) and through its instances (u_dut.u_chk.flag)

The UVM library

Names declared in the UVM library (uvm_driver, uvm_config_db, req, seq_item_port, …) resolve only if the UVM sources are in the IDE, either inside the project or attached as a library. Without them, everything declared in your own code still works, but renaming an override of a UVM method (such as build_phase) cannot be checked against the library. When UVM is attached as a library, it is never modified; when the UVM sources are part of the project itself, they are ordinary project code and a rename may change them.

Try it

1. In the sample project, open uvm/my_pkg.sv. In class my_driver, rename vif in virtual my_if vif; to m_vif (⇧F6 / Shift+F6, then Refactor). These change: the declaration, uvm_config_db#(virtual my_if)::get(this, "", "vif", m_vif), m_vif.req <= 1;, m_vif.data <= req.addr; and agt.drv.m_vif = null; in class my_env. The string "vif" stays. uvm/tb_top.sv is unchanged. Undo.
2. Rename the class my_item to bus_txn. The class, its end label, uvm_sequence #(bus_txn), uvm_driver #(bus_txn), bus_txn it; and bus_txn::type_id::create("it") change; the default argument "my_item" of the constructor stays. Undo.
3. Open uvm/my_if.sv and rename the interface my_if to bus_if. The end label, virtual bus_if vif; and uvm_config_db#(virtual bus_if)::get in uvm/my_pkg.sv, and the instance bus_if vif_inst(.clk(clk)); and uvm_config_db#(virtual bus_if)::set in uvm/tb_top.sv all change. Undo.