Live templates

Type an abbreviation and press Tab to insert a block of code. The editor then moves through the parts you usually change (names, clock, reset, conditions); press Tab to accept each one and Enter to finish. Code | Insert Live Template (⌘J / Ctrl+J) lists the templates that fit where the caret is.

Each template is offered only where its code belongs: design units and UVM classes at file level or in a package, processes, generate constructs and assertions in a module, interface or program, members and UVM phases in a class, and statements in procedural code (initial, always, functions and tasks). Nothing is offered elsewhere — inside a covergroup, struct, port list, comment or string, and not right after code that has a syntax error (the place around the caret is not known then). Statement templates are offered between the statements of a block; a single statement directly under if (…) or a case label without begin gets no template. Every template expands to code that parses without errors, in .sv, .svh and .v files, and is laid out by Reformat Code with your indent size.

acomb, then Tab — in a module

always_comb begin

end

Templates for UVM classes take the class name from the file name (my_driver.sv → class my_driver); members such as newc and cutils use the name of the class you are in. You can change and add templates in Settings | Editor | Live Templates, group SystemVerilog.

Templates

Design units and headers

Abbreviation	Inserts	Where
module	Module with parameters and ANSI ports	File level or package
interface	Interface with a clocking block and a modport	File level or package
package	Package	File level or package
program	Program	File level or package
class	Class with a constructor	File level or package, Module, interface or program, Class body
vclass	Virtual (abstract) class	File level or package, Module, interface or program, Class body
iclass	Interface class	File level or package, Module, interface or program, Class body
guard	Include guard for a header file	File level or package
imp	Wildcard package import	File level or package, Module, interface or program

Declarations

Abbreviation	Inserts	Where
tenum	Enum typedef	File level or package, Module, interface or program, Class body
tstruct	Packed struct typedef	File level or package, Module, interface or program, Class body
func	Function	File level or package, Module, interface or program, Class body
task	Task	File level or package, Module, interface or program, Class body
lp	Local parameter	File level or package, Module, interface or program, Class body

RTL and generate

Abbreviation	Inserts	Where
aff	always_ff with asynchronous active-low reset	Module, interface or program
affs	always_ff with synchronous reset	Module, interface or program
acomb	always_comb block	Module, interface or program
alatch	always_latch block	Module, interface or program
asg	Continuous assignment	Module, interface or program
init	initial block	Module, interface or program
gfor	Generate for loop	Module, interface or program
gif	Generate if / else	Module, interface or program
inst	Module instance with named port connections	Module, interface or program
clk	Clocking block	Module, interface or program
mp	Modport	Interface

Assertions and coverage

Abbreviation	Inserts	Where
prop	Property declaration	Module, interface or program
seq	Sequence declaration	Module, interface or program
ap	Concurrent assertion	Module, interface or program
asm	Assumption	Module, interface or program
cp	Cover property	Module, interface or program
cg	Covergroup with a coverpoint	Module, interface or program, Class body

Statements

Abbreviation	Inserts	Where
if	if block	Statements
ife	if / else block	Statements
case	case with default	Statements
ucase	unique case with default	Statements
casez	casez with default	Statements
for	for loop	Statements
foreach	foreach loop	Statements
while	while loop	Statements
dowhile	do / while loop	Statements
repeat	repeat loop	Statements
forever	forever loop	Statements
fork	fork / join	Statements
forkn	fork / join_none	Statements
forka	fork / join_any	Statements
be	begin / end block	Statements
disp	$display with format	Statements
ia	Immediate assertion	Statements

UVM statements

Abbreviation	Inserts	Where
uinfo	`uvm_info	Statements
uwarn	`uvm_warning	Statements
uerr	`uvm_error	Statements
ufatal	`uvm_fatal	Statements
cfgget	uvm_config_db get with a fatal error	Statements
cfgset	uvm_config_db set	Statements
create	Factory create	Statements
raise	Raise and drop an objection	Statements
rnd	randomize with an error check	Statements
start	Start a sequence on a sequencer	Statements

Class members and UVM phases

Abbreviation	Inserts	Where
new	Constructor	Class body
newc	UVM component constructor	Class body
newo	UVM object constructor	Class body
vfunc	Virtual function	Class body
vtask	Virtual task	Class body
cons	Constraint block	Class body
cutils	`uvm_component_utils for this class	Class body
outils	`uvm_object_utils for this class	Class body
build	UVM build_phase	Class body
connect	UVM connect_phase	Class body
run	UVM run_phase	Class body
report	UVM report_phase	Class body

UVM classes

Abbreviation	Inserts	Where
uitem	UVM sequence item	File level or package
useq	UVM sequence	File level or package
udrv	UVM driver	File level or package
umon	UVM monitor with an analysis port	File level or package
uagent	UVM agent (driver, sequencer, monitor)	File level or package
uenv	UVM environment	File level or package
usb	UVM scoreboard with an analysis import	File level or package
utest	UVM test	File level or package
ucomp	UVM component	File level or package
uobj	UVM object	File level or package

Try it

1. Open rtl/counter.sv from the sample project, put the caret at the end of assign done = is_done(state); and press Enter.
2. Type acomb and press Tab. An always_comb begin … end block is inserted with the caret inside it.
3. Press ⌘J (Ctrl+J) on an empty line in the module. The list offers module templates such as aff, gfor and ap, but not class or statement templates such as build or uinfo.
4. Open uvm/my_pkg.sv, put the caret at the end of the line virtual task run_phase(uvm_phase phase); in my_driver, press Enter, type uinfo and press Tab. A `uvm_info(get_type_name(), …) call is inserted.
5. In my_agent, put the caret after the endfunction of build_phase, press Enter, type connect and press Tab. A connect_phase function with its super.connect_phase(phase); call is inserted.