Syntax highlighting

Colors let you tell a port from a local variable, a parameter or a type at a glance, without hovering over each name. SystemVerilog Studio colors code in two layers:

• Tokens: keywords, numbers, strings, comments, operators, system tasks and macros are colored as you type.
• Names: every name is colored by what it is (a module, a port, a parameter, a class property, …). The plugin looks up where each name is declared, with the same name resolution as Go to Declaration, so a port and a local variable get different colors even though they look alike. Name colors appear a moment after you stop typing, like other code analysis in the IDE.

Try it

The steps use the sample project; open it and wait for indexing first. They change only your color settings, and the last step undoes that.

1. Pick a color scheme. Open Settings (⌘, on macOS / Ctrl+Alt+S on Windows/Linux; or File | Settings… on Windows/Linux, the menu named after your IDE and then Settings… on macOS). In the tree on the left, expand Editor and click Color Scheme. Remember which scheme is selected in the Scheme drop-down at the top, to come back to it in step 4, then choose SystemVerilog Studio Dark and click Apply. (A theme is the IDE’s overall look; a color scheme is the editor’s colors. SystemVerilog Studio Light works the same; its colors are in the table below.)

2. Read the colors. Open rtl/counter.sv. Names are colored once indexing has finished: counter_pkg.sv declares state_t, is_done and the enum members IDLE, COUNT and DONE, so they stay plain until then. In the Dark scheme:

   • keywords: module is gold (#E5C07B); if, begin and always_ff are purple (#C586C0); logic and input are blue (#569CD6);
   • names: counter (the module) and state_t (a type) are teal (#4EC9B0); is_done (a function call) is yellow (#DCDCAA); MAX (a parameter) and IDLE (an enum member) are bright blue (#4FC1FF); clk, rst_n, count, done (ports) and state (a variable) are pale blue (#9CDCFE).

   

   A port and a variable have the same color in this scheme (so do a parameter and an enum member): the plugin knows which is which and colors them in separate groups, so you can give each its own color. Step 3 does that for ports.

3. Change a color. In the tree on the left, expand Editor | Color Scheme and click SystemVerilog; the Scheme drop-down and its gear are at the top of this page, and a preview shows every group. Click the gear and choose Duplicate…, give the copy a name such as My Dark (so that your experiment does not change the bundled scheme); the copy is selected. In the list, expand Names and select Port. If Inherit values from is ticked, untick it; tick Foreground, click its color box and pick, for example, red; click OK (Settings closes). In rtl/counter.sv, clk, rst_n, count and done turn red, in the port list and where they are used in the code, and state stays pale blue.

4. Undo it. Reopen Settings, go to Editor | Color Scheme, choose the scheme you remembered in step 1 in the Scheme drop-down and click OK. The copy My Dark stays in the list until you delete it (the gear menu).

Keywords

Group	Examples
Design unit	module, endmodule, interface, program, package, class, endclass, checker, primitive, … (wherever the keyword appears, e.g. also in virtual interface and typedef class)
Declaration	function, endfunction, task, typedef, parameter, import, extends, nettype
Control flow	if, else, case, for, foreach, begin, end, fork, join, return, wait, unique0
Data type	logic, bit, int, real, string, reg, wire, uwire, signed
Direction and modifier	input, output, inout, ref, virtual, rand, soft, local, static, automatic
Process	always_ff, always_comb, initial, final, assign, posedge, negedge
Other keywords	every other IEEE 1800-2017 keyword, for example this, super, null, new, std, and property operators such as until and implies

These also have their own colors:

• system tasks and functions ($display, $clog2, $urandom, any $name);
• macros and compiler directives (`define, `uvm_info, and `timescale 1ns/1ps, `default_nettype none, `resetall, `celldefine, `pragma, … with their arguments, up to a trailing comment);
• strings and numbers (8'h10, 3.14, '0);
• operators (==, <=, ? :, ::, @, #, ##, ++, +:, …);
• comments, and attributes ((* keep = "true" *), listed as Attribute in the color settings).

The code of an inactive `ifdef branch is greyed out (listed as Inactive code; see Conditional compilation).

Names

Color group	Examples
Module, interface, program, package	counter in module counter and in counter u1(...); counter_pkg in import counter_pkg::*;
Class	shape in class shape, extends shape, shape s;
Type	state_t (typedef), type parameters, modports
Function or task declaration	is_done in function logic is_done(...); build_phase in an out-of-block function void my_drv::build_phase(...)
Function or task call	is_done(state), s.area(), super.build_phase(phase), uvm_config_db#(int)::get(...)
Port	clk in the port list and in the module body
Parameter	MAX in parameter int MAX = 10 and where it is used
Enum member	IDLE
Class property or struct field	side in real side; and in side * side
Variable, net or genvar	state in state_t state;
Function or task argument	s in is_done(state_t s)
Instance or clocking block	u_counter in rtl/top.sv
Label	seq in begin : seq and end : seq (its color is close to plain text in the Dark scheme)

A name that cannot be resolved keeps the plain text color, except in positions where its role is clear:

• a type (extends uvm_driver) or class prefix (uvm_config_db#(int)::) is colored as a class,
• a call (f(...), obj.f(...), C::f(...)) as a function call,
• a package in import uvm_pkg::*; as a package,
• the module name of an instantiation as a module.

That way UVM code keeps its colors even when the UVM library is not in the project. Named connections to an unknown module (.clk(clk)) are not colored as calls.

SystemVerilog Studio color schemes

The plugin includes two editor color schemes. Related groups share a color family:

Group	Dark	Light
Design unit keywords (module, class, …)	gold	dark gold
Control flow and process keywords, macros	purple	purple
Declaration, data type and modifier keywords	blue	blue
Module, class and type names	teal	teal
Functions and system tasks	yellow	brown
Ports, variables, properties, arguments, instances	light blue	dark blue
Parameters and enum members	bright blue	medium blue
Strings	orange	red
Numbers	light green	green
Comments	green	green
Inactive code	grey	light grey

Scheme	Based on
SystemVerilog Studio Dark	Darcula
SystemVerilog Studio Light	the default light scheme

Select one in Settings | Editor | Color Scheme with the Scheme drop-down. They only set the SystemVerilog colors; everything else (other languages, the editor background, the rest of the IDE) comes from the base scheme.

Changing the colors

Open Settings | Editor | Color Scheme | SystemVerilog. Every group above is listed there, with a preview. By default the colors follow your IDE theme’s standard categories (keyword, function, constant, field, …); module, class and type names and ports have their own colors in the light and dark themes.

Tip

Colors are part of the color scheme: to keep your changes when you switch themes, save them under a scheme of your own: click the gear next to the Scheme drop-down, then Duplicate…, first.

If it doesn’t work

You see	Likely cause	What to do
Nothing is colored	The file is not a SystemVerilog file (check its extension: .sv, .svh or .v), or the plugin is disabled	See Installation
Keywords are colored but names are not, or a name stays plain	Indexing has not finished, or the name is not declared anywhere in the project (a library such as UVM that is not in the project)	Wait for the progress bar at the bottom right; see the unresolved-name rules under Names
Two names look the same	They are in groups that share a color (a port and a variable, a parameter and an enum member)	Expected; give a group its own color under Settings | Editor | Color Scheme | SystemVerilog (step 3)
You changed a color and nothing happened	The color was set on another scheme, or Foreground is not ticked	Check that your copy (for example My Dark) is selected in the Scheme drop-down
The Scheme drop-down has no SystemVerilog Studio scheme	The plugin is not installed or is disabled	See Installation
Code is grey	It is in an inactive `ifdef branch	See Conditional compilation

Limitations

• In a hierarchical path that starts at a top-level module name (top.u_sub.cnt), the first name keeps the plain text color (see Known limitations).
• Names inside macro arguments are not colored.
• Words that became keywords in IEEE 1800-2009 and later (soft, weak, global, …) get the keyword color even in older Verilog files that use them as names.
• Names of assertion properties and sequences (property p; … endproperty) are not colored yet.