Release notes

2026.2.5 (2026-10-23)

New

Create Compile File… (Tools menu, and the editor’s and the Project view’s right-click menus) writes a compile file (.f) from a top module: the files it needs, in compile order. See Compile file.
Usage data (optional): the first time you open a project with SystemVerilog files, SystemVerilog Studio asks once whether it may send usage data (which features and tools are used, with a random install ID; never your code, file or project names, or anything you type). Nothing is sent until you say yes; you can change your answer in Settings | Tools | SystemVerilog Studio Usage Data. See Usage data.
For coding agents: write instances of your modules. sv_module_instance gives an instance of a module, interface or program as text, the way code completion writes it (following Code Style | SystemVerilog | Instances): by default every parameter at its default and every port named and left empty. It changes no file.
sv_insert_instance puts that instance into a file before a line the agent names, each port connected to the signal of the same name declared above it, under a name not yet used there. It is a dry run that shows a diff unless the agent passes apply=true, which writes and saves it as one undoable command (Edit | Undo). It refuses places where an instance cannot start (a comment, a port list, an expression, outside a module). If the file has unsaved changes in the editor, the dry run shows the editor’s text and nothing is written until you save or discard them.
Both tools take options: parameters and connections to set values, array_count for an array of instances in a generate loop, instances for up to 32 instances in one call, and declare_nets to declare and connect a net for each port left unconnected. See Coding agents (MCP).

2026.2.4 (2026-10-04)

New

For coding agents: sv_create_compile_file makes a compile file (.f) from a top module when a project has none: the files the top needs, in an order that compiles, with the files defining the macros they use without including them; a dry run first, then written and made the project’s compile file. See Coding agents (MCP).
Running tools, rewritten guide: one page each for Run configurations, Verilator, Icarus Verilog, Waveform viewer and Emacs verilog-auto, each with a Try it that builds and runs the sample project’s new testbench.

Fixed

Verilator and Icarus Verilog run configurations pass Options after the compile file, so a testbench file there is compiled after the design; with Icarus on macOS such a run lost the compile file.
The Run tool window showed each command line of a run configuration twice.
The balloon “slang did not compile the design: no compile file” no longer appears on every project open; slang runs by itself once a compile file is chosen.
sv_project_info said elaboration was unavailable in every project.
slang: Download slang and slang-server shows its progress; the status-bar item appears once a compile file is chosen; “slang did not compile the design” opens the page that fixes the reason.

2026.2.3 (2026-10-04)

New

Compiler checks with slang: install the open-source slang compiler from the plugin’s settings, and the whole design is compiled after each save; slang’s errors and warnings appear in the editor next to the plugin’s own, and the status bar shows the result. See Compiler checks (slang).
Design Hierarchy: the elaborated design in a tool window — every instance, generate blocks unrolled, parameters with the values they really get. Without slang-server it shows the static hierarchy. See Design hierarchy.
For coding agents: sv_hierarchy gives the elaborated design (and searches it, or lists its modules), sv_check adds slang’s results with a verdict per file, and sv_project_info says which slang tools are installed. sv_elaborated_drivers traces what drives a signal across the elaborated hierarchy, sv_apply_fix applies one of the plugin’s quick fixes (as a diff first), sv_outline gives a file as a compact outline instead of its text, and sv_run runs a Verilator or Icarus run configuration and returns its problems parsed — off by default, turned on in Settings | Languages & Frameworks | SystemVerilog | Coding Agents. See Coding agents (MCP).

2026.2.2 (2026-10-03)

New

Who drives this signal? Find Usages groups a signal’s usages as Value write and Value read, and the coding-agent tool sv_drivers lists what drives a signal and what reads it, through instance ports into children and up to parents. See Find Usages and Coding agents (MCP).
Check an edit before it is written: sv_check with content checks the text an agent is about to write, as that file, without writing it.
Instructions for coding agents: a Claude Code skill and an AGENTS.md section saying which sv_ tool to use when. See Coding agents (MCP).
Suggestions for misspelled members: 'scal' is not a member of class 'square'; did you mean 'scale'?, with a Change to quick fix. See Unknown members.
Connection widths of enums, typedefs and packed structs are compared, and a positional connection list that stops before an output is reported. See Instance connections.
Typos in an instance’s parameter values (#(.Width(Widht))) are reported. See Undeclared names.
sv_module_interface lists the parameters and ports in inactive `ifdef branches; sv_members, sv_instances, sv_module_interface and sv_rename keep their answers small on large or copied designs.
Instances a macro creates are checked: a missing input or a port the module does not have in a `define body that instantiates a module is reported in the body and at every call of the macro. See Instance connections.
Macros for coding agents: sv_find_references finds a macro’s calls (also those an `ifdef leaves out, listed apart), and sv_expand_macro says which `ifdef names its expansion tested and in which branch the `define it used sits. See Coding agents (MCP).
sv_members for coding agents: what a class has, with its base classes, a struct’s fields and an enum’s literals, so an agent writing a sequence does not have to read the testbench’s files. See Coding agents (MCP).
Misspelled base classes are reported, with the nearest class suggested. See Undeclared names.

Fixed

specparam: a gate delay naming a specparam is no longer reported as an implicit net.
Macros that create instances show only the problems of the `ifdef branches a call takes.
UVM testbenches: misspelled names in code that imports UVM are reported now; the check used to give up on UVM’s own macro files.
ifdef in a module’s parameters or ports: a name written in no branch is reported as unknown.
Designs copied into several trees: each tree’s names resolve to its own copy; Find Usages and Rename no longer mix them.

2026.2.1 (2026-10-01)

New

Tools for coding agents: Claude Code, Codex, Cursor, Junie and other agents connected to the IDE’s MCP server can ask what SystemVerilog Studio knows instead of guessing from the text — declarations, a module’s ports and parameters, the uses of a declaration, macro expansions, the instance hierarchy and the problems in a file — and can expand verilog-mode AUTOs and rename a declaration with every use, as a dry run first. Results say what could not be checked (a package, an include, a macro or a base class the project does not have, such as UVM not configured), so a clean result is not mistaken for a pass. See Coding agents (MCP).
Undeclared names: a misspelled signal, parameter or enum value is an error with the nearest declared name as a fix (ST_IDEL → ST_IDLE); a typo that creates an implicit net is a warning. See Undeclared names.
Unknown members: a misspelled class member or struct field after . is an error. See Unknown members.
Call arguments: a call that leaves out a required argument, gives too many, or names one that does not exist is an error. See Call arguments.
Unknown modules: an instance of a module no definition is known for is an error. See Instance connections.
Expand Macro: what a macro call expands to, laid out and highlighted, from Code | Expand Macro, a gutter icon on the call or Quick Documentation. See Macros.
verilog-mode AUTOs: Code | Expand AUTOs writes what Emacs verilog-mode’s AUTOINST, AUTO_TEMPLATE, AUTOWIRE, AUTOLOGIC, AUTOINPUT, AUTOOUTPUT, AUTOINOUT and AUTORESET stand for, as verilog-mode does; Code | Delete AUTOs removes it. See verilog-mode AUTOs.
Connection widths: a port and the signal connected to it that differ in width (both constant) get a warning. See Instance connections.
Declare missing signals: Alt+Enter on an instance declares the signals it connects that nobody declared, with the types of their ports. See Instance connections.
How instances are written: Settings | Editor | Code Style | SystemVerilog | Instances (also .editorconfig) says how a completed instance is written: connections by name, implicit or .*, alignment and the instance name pattern. See Code completion.
Older IDEs: SystemVerilog Studio now installs in IntelliJ-based IDEs from 2025.2.2.

Changed

Included files see where they are included: a class file `included into a package resolves the package’s imports and declarations, and a package sees what its included files declare. See How names are resolved.
Macros: module, port and parameter names in a `define body that instantiates a module are found by Find Usages and changed by Rename; names that `uvm_component_utils and other class-level macros declare (type_id, get_type) resolve and complete.
Parameterized base classes: members reached through a handle typed by a class type parameter (CFG_T cfg) resolve to the class a subclass binds it to.
More real-world code parses: based numbers with white space or a macro value (16'h 4001, 32'h`DM_ADDR), foreach (a[i][j]), $fatal("message"), files that hold only part of a module or class body and are included into it.
Rename and AUTO_TEMPLATEs: renaming a module also renames it at the head of verilog-mode AUTO_TEMPLATE comments, so Expand AUTOs still applies them. See Rename.
Sequence and property names are declarations: Go to Declaration, Find Usages and Rename find them. Names after a class specialization (cfg#(W)::type_id::create) resolve.
No “not imported” warning where an imported package cannot be found (a package generated at build time).
After an update that changes how files parse, the plugin’s indexes are rebuilt, so no stale results remain.
Code completion knows where you are: after . it lists the members of that object (inherited ones too), after :: the members of the package or class, in an instance the ports and parameters not yet connected, in a call the arguments of that function or task, after import the packages, after extends, typedef or a direction the types, and in a non-ANSI port declaration the ports of the header. Elsewhere it lists only the names visible at the caret, closest first, with each variable’s type and each function’s arguments; names your file uses but the IDE cannot see declared come last. The list opens by itself after ., ::, $ and a backtick; after $ it offers the system tasks and functions with their arguments. After . on a string, enum, array, queue or object it also offers the built-in methods (len(), push_back(), randomize(), …), and local/protected members only where they are accessible. Keywords that fit the position come first: always_ff in a module, rand in a class, if in a statement, posedge in @(…), the end keyword you need. Choosing a function, task or macro inserts its parentheses. See Code completion.
Instance connections are checked as you type: a port or parameter the module does not have, a port connected twice, an input left out, a parameter that must be set; Alt+Enter connects the missing ports. See Instance connections.
Instance names: after counter completion offers u_counter (numbered if the name is taken).
Connections: in u(.count(, completion lists the signals that fit the port first — the one of the same name, then those of the same type and a similar name.
Instances by completion: type a module’s name where a module item goes and choose the instance item — the whole instance is inserted with its parameters and its ports connected to your signals of the same name; Tab moves through the name, the parameters and the connections. See Code completion.
Parameter info shows the arguments of a call, the ports of an instance and the parameters of a parameter list while you type them, with the current one highlighted (⌘P/Ctrl+P, or after typing (). See Parameter info.
Rename reports a conflict when a name would be captured by an instance that bind adds to the module.

2026.2.0 (2026-09-26)

Fixed

Broken blocks keep their contents: a generate block, begin/fork block, covergroup, property, sequence or clocking block with a missing end keyword or a broken item keeps its items while you type; deeply nested assertion or generate code can no longer make parsing hang.
SystemVerilog Assertions parse in full: sequences and properties follow the IEEE 1800 operator precedence — sequences with arguments, parenthesized sub-sequences, multi-clock sequences, first_match, local variables, if … else and case in properties — and a broken assertion no longer hides the code after it.
Parsing is about 20 times faster, and real-world code parses correctly: every file of the UVM 1800.2-2017 library opens without syntax errors (with the macros each file defines, see Conditional compilation). Expressions follow the IEEE 1800 operator precedence, including x inside {…}, y++, this.a.b(), C#(T)::x, casts such as int'(x) and void'(f()), with clauses, streaming and std::randomize.
A syntax error stays where it is: a statement or declaration that does not parse is skipped up to its ; (or the next declaration), and the rest keeps its place, highlighting and navigation — the methods after a broken class property stay members of the class, a broken port or argument leaves the others in its list, a port list you are still typing (no ) yet) keeps its module, and a stray end keyword (endclass, end, …) is reported on its own. A unit without its endmodule / endclass / endpackage / endprogram ends before the next module, program or package. Because nesting is legal there, a class that follows a module, program or package, and an interface that follows a module or interface, are taken into it; a class ends before a following class that does not close inside it.
Macro calls as statements: after `uvm_info(...) without a ;, the next line keeps its meaning (an assignment is no longer read as a declaration). Empty macro arguments and arguments such as `uvm_do_with(req, { addr == 5; }) no longer cause syntax errors.
Macros and conditional compilation: `elsif, `ifdef inside port lists and bodies, and multi-line `define bodies no longer cause syntax errors.
`timescale and other line directives (`default_nettype, `resetall, `celldefine, `pragma, …) no longer stop navigation, highlighting and the other features for the rest of the file.

Removed

The SystemVerilog module type, its module settings editor and the Create Interface UVC / Create UVC From Interface generators. SystemVerilog support never depended on the module type: a project created with it may report the module type as unknown, and its SystemVerilog files keep every feature.

New

Legacy Verilog and more SystemVerilog parses: functions without a return type (function f();, function automatic k; with input a; in the body), gate primitives (and, nand, bufif0, nmos, tran, pullup, …, also as arrays), attributes such as (* keep = "true" *) (colored as Attribute), drive strengths on assign, and instances with a delay (my_udp #5 u(...)).
Checkers and user-defined primitives: checker … endchecker and primitive … endprimitive (with their table … endtable) parse, fold, are indented by Reformat Code and appear in the Structure View and in Navigate | Symbol.
Run your tools. New run configurations for Verilator (lint, build, or build and run the simulation), Icarus Verilog, a waveform viewer (Surfer or GTKWave) and Emacs verilog-auto. They use the project’s compile file (.f) and its defines, and every file and line in the tool output is a link. See Simulators and waveform viewers.
Conditional compilation: only the active branch of an `ifdef is code; the others are greyed out and ignored by navigation, completion and the Structure View. Macros `defined earlier in the file count, and so do the defines of your compile file (.f) and of Settings | Languages & Frameworks | SystemVerilog, the macros of the headers a file includes and of the files before it in the compile file. See Conditional compilation. Inactive code folds.
New SystemVerilog File adds a Package kind and checks that the name is a SystemVerilog identifier. See New file from a template.
Spell-checking checks strings and declared names, each name once where it is declared. See Spell-checking.
Structure View lists the ports, parameters, nets, variables, typedefs, instances, subroutines, constraints, modports, clocking and generate blocks of every module, interface, package and class. See Structure View.
Folding collapses the body of every multi-line scope and multi-line comments. See Folding.
Reformat Code indents every kind of scope — including case items, fork … join, generate blocks, covergroups, clocking blocks and constraint bodies — and the statement under an if or loop. See Reformat Code.
Live templates: 80 templates for SystemVerilog and UVM, offered only where their code belongs. See Live templates.
Time literals and coverage syntax: #10ns, timeunit 1ns;, #1step, labeled coverpoints (cp: coverpoint x;), bins ranges ({[0:3], 20}), covergroup options (option.per_instance = 1;), with function sample(…), cross selections (binsof(cp.low), binsof … intersect {…} && …), clocked sequences (@(posedge clk) a ##1 b), repetitions (req |-> ack[*1:$], b[->1:3], b[=1:3], b[+]), unbounded delays (##[*], ##[+]), first_match(…), transition bins ((1 => 2[*3] => 3)) and default input #1step output #1; in clocking blocks no longer cause syntax errors.
Interface classes across files: implements and extends find an interface class declared in another file.
Nested classes: a class or interface class declared inside a class is a member of it; outer::inner and uses inside the outer class navigate to it.
Macros: completion after a backtick, Quick Documentation, Go to Declaration, Find Usages and Rename for `define macros, from calls, `ifdef, `undef and other macro bodies. Names passed to a macro, such as the class in `uvm_component_utils(my_driver), are navigable and renamed with their declaration. See Macros.
Find Usages and Rename for every declared construct — modules, interfaces, programs, packages, classes, interface classes, functions, tasks, modports, clocking blocks, ports (ANSI and Verilog-95), parameters, type parameters, variables, nets, typedefs, enum and struct members, genvars, instances and named/generate blocks, across files. See Supported constructs.
Scope-aware name resolution following IEEE 1800: enclosing scopes, base classes, imports (explicit before wildcard), member access chains, generate blocks, clocking blocks and bind.
Rename keeps related declarations together: virtual method override families, Verilog-95 port declarations, end labels, implicit .clk connections, labels shared by exclusive generate branches.
Rename conflict detection before any file is changed. See Rename conflicts.
UVM testbench support for virtual interfaces, uvm_config_db, type_id::create, parameterized base classes and phase methods. See UVM testbenches.
Richer syntax highlighting: keyword groups (declarations, control flow, data types, modifiers, processes), all system tasks, macros, and names colored by what they are: modules, classes, types, functions, ports, parameters, enum members, properties, variables, instances and labels. See Syntax highlighting.
SystemVerilog Studio Dark and Light color schemes in the style of popular VS Code themes, with separate color families for control flow, declarations and types, type names, functions, signals and constants.
Go to Symbol lists modules, interfaces, programs, packages, classes, functions and tasks (not every name in the project). See Go to Symbol.
Code completion for keywords, the modules, interfaces, programs, packages, classes, functions and tasks of the project (labelled by kind) and the names of the current file. See Code completion.
Closing keywords on Enter: after begin, fork, case (…) or a module, class, function or task header, Enter adds the missing end, join, endcase, endmodule, endfunction, … See Brackets, blocks and quotes.
Enter indents to the surrounding scope (module, class, function, begin/end) and one level in after if (…), else, loops, case (…), always/initial — also while the code is still incomplete; the default indent is now 2 spaces (Reformat Code re-indents 4-space files; to keep 4, set Settings | Editor | Code Style | SystemVerilog | Indent to 4). See Indentation.
Names from packages that are not imported: a warning with a quick fix that adds the import, and Go to Declaration still opens the package member. See Go to Declaration.
Faster indexing: only declarations are stored in the index, not every name occurrence.
Commenting with line (//) and block (/* */) comments.
Matching of brackets and block keywords (begin/end, fork/join*, case/endcase, module, class, package, program, generate, covergroup), automatic closing of ( and ".
License notification with a Register… action.

Fixed

program and modport declarations failed to parse; ANSI interface ports (bus_if bus) were misparsed.
Names in constant expressions ([W-1:0]) could not be navigated or renamed.
disable fork;, wait fork; and typedef class c; were highlighted as unmatched blocks.

Compatibility

Requires IDE 2026.2 or newer. See Compatibility.