Release notes

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Changed

Code completion knows where you are: after . it lists the members of that object (inherited ones too), after :: the members of the package or class, in an instance the ports and parameters not yet connected, in a call the arguments of that function or task, after import the packages, after extends, typedef or a direction the types, and in a non-ANSI port declaration the ports of the header. Elsewhere it lists only the names visible at the caret, closest first, with each variable’s type and each function’s arguments; names your file uses but the IDE cannot see declared come last. The list opens by itself after ., ::, $ and a backtick; after $ it offers the system tasks and functions with their arguments. After . on a string, enum, array, queue or object it also offers the built-in methods (len(), push_back(), randomize(), …), and local/protected members only where they are accessible. Keywords that fit the position come first: always_ff in a module, rand in a class, if in a statement, posedge in @(…), the end keyword you need. Choosing a function, task or macro inserts its parentheses. See Code completion.
Instance connections are checked as you type: a port or parameter the module does not have, a port connected twice, an input left out, a parameter that must be set; Alt+Enter connects the missing ports. See Instance connections.
Instance names: after counter completion offers u_counter (numbered if the name is taken).
Connections: in u(.count(, completion lists the signals that fit the port first — the one of the same name, then those of the same type and a similar name.
Instances by completion: type a module’s name where a module item goes and choose the instance item — the whole instance is inserted with its parameters and its ports connected to your signals of the same name; Tab moves through the name, the parameters and the connections. See Code completion.
Parameter info shows the arguments of a call, the ports of an instance and the parameters of a parameter list while you type them, with the current one highlighted (⌘P/Ctrl+P, or after typing (). See Parameter info.
Rename reports a conflict when a name would be captured by an instance that bind adds to the module.

2026.2.0 (2026-09-26)

Fixed

Broken blocks keep their contents: a generate block, begin/fork block, covergroup, property, sequence or clocking block with a missing end keyword or a broken item keeps its items while you type; deeply nested assertion or generate code can no longer make parsing hang.
SystemVerilog Assertions parse in full: sequences and properties follow the IEEE 1800 operator precedence — sequences with arguments, parenthesized sub-sequences, multi-clock sequences, first_match, local variables, if … else and case in properties — and a broken assertion no longer hides the code after it.
Parsing is about 20 times faster, and real-world code parses correctly: every file of the UVM 1800.2-2017 library opens without syntax errors (with the macros each file defines, see Conditional compilation). Expressions follow the IEEE 1800 operator precedence, including x inside {…}, y++, this.a.b(), C#(T)::x, casts such as int'(x) and void'(f()), with clauses, streaming and std::randomize.
A syntax error stays where it is: a statement or declaration that does not parse is skipped up to its ; (or the next declaration), and the rest keeps its place, highlighting and navigation — the methods after a broken class property stay members of the class, a broken port or argument leaves the others in its list, a port list you are still typing (no ) yet) keeps its module, and a stray end keyword (endclass, end, …) is reported on its own. A unit without its endmodule / endclass / endpackage / endprogram ends before the next module, program or package. Because nesting is legal there, a class that follows a module, program or package, and an interface that follows a module or interface, are taken into it; a class ends before a following class that does not close inside it.
Macro calls as statements: after `uvm_info(...) without a ;, the next line keeps its meaning (an assignment is no longer read as a declaration). Empty macro arguments and arguments such as `uvm_do_with(req, { addr == 5; }) no longer cause syntax errors.
Macros and conditional compilation: `elsif, `ifdef inside port lists and bodies, and multi-line `define bodies no longer cause syntax errors.
`timescale and other line directives (`default_nettype, `resetall, `celldefine, `pragma, …) no longer stop navigation, highlighting and the other features for the rest of the file.

Removed

The SystemVerilog module type, its module settings editor and the Create Interface UVC / Create UVC From Interface generators. SystemVerilog support never depended on the module type: a project created with it may report the module type as unknown, and its SystemVerilog files keep every feature.

New

Legacy Verilog and more SystemVerilog parses: functions without a return type (function f();, function automatic k; with input a; in the body), gate primitives (and, nand, bufif0, nmos, tran, pullup, …, also as arrays), attributes such as (* keep = "true" *) (colored as Attribute), drive strengths on assign, and instances with a delay (my_udp #5 u(...)).
Checkers and user-defined primitives: checker … endchecker and primitive … endprimitive (with their table … endtable) parse, fold, are indented by Reformat Code and appear in the Structure View and in Navigate | Symbol.
Run your tools. New run configurations for Verilator (lint, build, or build and run the simulation), Icarus Verilog, a waveform viewer (Surfer or GTKWave) and Emacs verilog-auto. They use the project’s compile file (.f) and its defines, and every file and line in the tool output is a link. See Simulators and waveform viewers.
Conditional compilation: only the active branch of an `ifdef is code; the others are greyed out and ignored by navigation, completion and the Structure View. Macros `defined earlier in the file count, and so do the defines of your compile file (.f) and of Settings | Languages & Frameworks | SystemVerilog, the macros of the headers a file includes and of the files before it in the compile file. See Conditional compilation. Inactive code folds.
New SystemVerilog File adds a Package kind and checks that the name is a SystemVerilog identifier. See New file from a template.
Spell-checking checks strings and declared names, each name once where it is declared. See Spell-checking.
Structure View lists the ports, parameters, nets, variables, typedefs, instances, subroutines, constraints, modports, clocking and generate blocks of every module, interface, package and class. See Structure View.
Folding collapses the body of every multi-line scope and multi-line comments. See Folding.
Reformat Code indents every kind of scope — including case items, fork … join, generate blocks, covergroups, clocking blocks and constraint bodies — and the statement under an if or loop. See Reformat Code.
Live templates: 80 templates for SystemVerilog and UVM, offered only where their code belongs. See Live templates.
Time literals and coverage syntax: #10ns, timeunit 1ns;, #1step, labeled coverpoints (cp: coverpoint x;), bins ranges ({[0:3], 20}), covergroup options (option.per_instance = 1;), with function sample(…), cross selections (binsof(cp.low), binsof … intersect {…} && …), clocked sequences (@(posedge clk) a ##1 b), repetitions (req |-> ack[*1:$], b[->1:3], b[=1:3], b[+]), unbounded delays (##[*], ##[+]), first_match(…), transition bins ((1 => 2[*3] => 3)) and default input #1step output #1; in clocking blocks no longer cause syntax errors.
Interface classes across files: implements and extends find an interface class declared in another file.
Nested classes: a class or interface class declared inside a class is a member of it; outer::inner and uses inside the outer class navigate to it.
Macros: completion after a backtick, Quick Documentation, Go to Declaration, Find Usages and Rename for `define macros, from calls, `ifdef, `undef and other macro bodies. Names passed to a macro, such as the class in `uvm_component_utils(my_driver), are navigable and renamed with their declaration. See Macros.
Find Usages and Rename for every declared construct — modules, interfaces, programs, packages, classes, interface classes, functions, tasks, modports, clocking blocks, ports (ANSI and Verilog-95), parameters, type parameters, variables, nets, typedefs, enum and struct members, genvars, instances and named/generate blocks, across files. See Supported constructs.
Scope-aware name resolution following IEEE 1800: enclosing scopes, base classes, imports (explicit before wildcard), member access chains, generate blocks, clocking blocks and bind.
Rename keeps related declarations together: virtual method override families, Verilog-95 port declarations, end labels, implicit .clk connections, labels shared by exclusive generate branches.
Rename conflict detection before any file is changed. See Rename conflicts.
UVM testbench support for virtual interfaces, uvm_config_db, type_id::create, parameterized base classes and phase methods. See UVM testbenches.
Richer syntax highlighting: keyword groups (declarations, control flow, data types, modifiers, processes), all system tasks, macros, and names colored by what they are: modules, classes, types, functions, ports, parameters, enum members, properties, variables, instances and labels. See Syntax highlighting.
SystemVerilog Studio Dark and Light color schemes in the style of popular VS Code themes, with separate color families for control flow, declarations and types, type names, functions, signals and constants.
Go to Symbol lists modules, interfaces, programs, packages, classes, functions and tasks (not every name in the project). See Go to Symbol.
Code completion for keywords, the modules, interfaces, programs, packages, classes, functions and tasks of the project (labelled by kind) and the names of the current file. See Code completion.
Closing keywords on Enter: after begin, fork, case (…) or a module, class, function or task header, Enter adds the missing end, join, endcase, endmodule, endfunction, … See Brackets, blocks and quotes.
Enter indents to the surrounding scope (module, class, function, begin/end) and one level in after if (…), else, loops, case (…), always/initial — also while the code is still incomplete; the default indent is now 2 spaces (Reformat Code re-indents 4-space files; to keep 4, set Settings | Editor | Code Style | SystemVerilog | Indent to 4). See Indentation.
Names from packages that are not imported: a warning with a quick fix that adds the import, and Go to Declaration still opens the package member. See Go to Declaration.
Faster indexing: only declarations are stored in the index, not every name occurrence.
Commenting with line (//) and block (/* */) comments.
Matching of brackets and block keywords (begin/end, fork/join*, case/endcase, module, class, package, program, generate, covergroup), automatic closing of ( and ".
License notification with a Register… action.

Fixed

program and modport declarations failed to parse; ANSI interface ports (bus_if bus) were misparsed.
Names in constant expressions ([W-1:0]) could not be navigated or renamed.
disable fork;, wait fork; and typedef class c; were highlighted as unmatched blocks.

Compatibility

Requires IDE 2026.2 or newer. See Compatibility.