Spell-checking

The IDE’s Typo inspection checks, in SystemVerilog files:

• comments and string literals;
• the names that declarations introduce — modules, classes, signals, functions, `define macro names, … — split into words at _ and at case changes (rx_fifo_lenght → lenght).

A name is checked where it is declared, not at each use, so a misspelt name is reported once; Alt+Enter on it offers Rename to …, which renames the declaration and all its uses. In strings, escape sequences (\n, \t) and format specifiers (%0d) are not words. Keywords, system tasks, attributes ((* mark_debug = "true" *)) and compiler directives (`timescale, `ifdef …) are not checked, and neither is the code of an inactive `ifdef branch (Conditional compilation). A typo can also be added to the dictionary.

Try it

1. Open rtl/counter.sv from the sample project.
2. Above state_t state;, type // the recieved count. recieved is underlined as a typo.
3. Press Alt+Enter and choose received.