Supported constructs

Every construct below supports Go to Declaration, Find Usages and Rename.

Construct	Declaration	Usages that are recognized
Module	module counter … (ANSI and Verilog-95 headers)	Instantiations, bind targets, end labels
Interface	interface my_if …	Interface ports, virtual my_if, instantiations, type arguments, end labels
Program	program p …	Instantiations, end labels
Package	package pkg;	import pkg::*;, import pkg::x;, pkg::x, end labels
Class, interface class	class c extends b;, interface class i;, a class inside a class	Types, extends, implements, #(c), c::x, c::type_id, outer::inner, typedef class c;, end labels
Function, task	Including extern, out-of-block function c::f(), DPI imports	Calls, super.f(), obj.f(), disable t;, end labels, return-value assignment f = …
Virtual method	virtual function …	Renamed together with all overrides
Modport	modport mp(...)	my_if.mp in ports and virtual interface types
Clocking block	clocking cb @(...)	vif.cb, vif.cb.req, default clocking cb;, modport … (clocking cb), endclocking : cb
Port	ANSI and Verilog-95 (input a; wire a;)	Body, named connections .a(x), implicit .a, inst.a
Parameter, localparam, type parameter	parameter int W = 8, parameter type T = int	Expressions, ranges, named overrides #(.W(16)), and names used as values in #(W)
Variable, net	logic a;, wire w;, class properties	Expressions, member access obj.a, this.a, q[i].a, hierarchical u1.a, g[0].a
Function/task argument	input int x	Body, named arguments f(.x(1))
Typedef	typedef … t;	Types, member access through typedef’d class handles
Enum member	typedef enum {IDLE, …}	Expressions, pkg::IDLE, via imports
Struct/union field	struct { logic a; } s;	s.a, s.inner.field
Genvar	genvar i;, for (genvar i = …)	Loop bodies
Instance	counter u1(...);	u1.sig, g[0].u1.sig
Named block, generate block	begin : seq, for (…) begin : g_lane	End labels, disable seq;, g_lane[0].x

Loop variables, foreach indices, constructor arguments and other locals are visible only where the language makes them visible; a local never gets confused with a module signal or class property of the same name.

Positional connections and overrides (sub u(a, b);, sub #(4) u();) are not linked to the port or parameter they connect to, so renaming a port or parameter does not touch them (they stay correct).

Names are case-sensitive: Data and data are different names.

Other constructs

These parse and appear in the Structure View and Navigate | Symbol, but do not take part in Go to Declaration, Find Usages or Rename yet: checkers (checker … endchecker) and user-defined primitives (primitive … endprimitive). Named gate primitives (and g1 (y, a, b);) are listed as instances in the Structure View, and their terminals are ordinary expressions (Go to Declaration on y works). Verilog-95 forms parse too: functions and tasks with their ports declared in the body (function automatic k; input a; …), functions without a return type (function f();), instance arrays (sub u [3:0] (…)), attributes (* … *) (ignored), drive strengths and delays on assign and on instances.

Code with syntax errors

The parser keeps the structure of a file while you type. A statement, declaration, port or argument that does not parse is marked as one error and skipped up to its ; (or the next declaration); everything after it keeps its place, so navigation, Find Usages and Rename keep working in the rest of the file:

• the methods after a broken class property stay members of the class;
• a broken port or argument (a,,b) leaves the others in its list, and a port list you are still typing (no ) yet) keeps its module;
• a header without its ; keeps the unit’s name and items;
• a stray end keyword (end, endclass, endtask, …) is reported on its own — also a foreign one inside an initial or always block (endfunction), which keeps its later statements;
• a generate block, begin/fork block, covergroup (and its coverpoints and crosses), property, sequence or clocking block with a missing end keyword or a broken item keeps its items;
• a statement without its ; before a declaration (x <= 1 then logic z;) does not take the declaration in;
• a unit without its end keyword ends before the next module, program or package.

On the UVM 1800.2-2017 library, typical editing mistakes (a deleted token, a stray ;, end, ) or endclass, a missing ;) keep more than 98.5 % of the declarations in place. See Known limitations for the constructs that are not parsed yet.