Sample project
Every feature page ends with a Try it section: short steps you can follow in the IDE, with the result you should see. They use this sample project.
- Download sample-project.zip and unzip it.
- In the IDE, choose File | Open… and select the unzipped folder.
- Wait for indexing to finish.
Contents
Section titled “Contents”| Folder | Files | What it shows |
|---|---|---|
rtl/ |
counter_pkg.sv, counter.sv, top.sv, legacy_reg.v |
A package with an enum and a function, a parameterized counter, a top level with named and implicit (.clk) port connections and a generate loop, a Verilog-95 style module |
/ |
sim.f |
A compile file listing the design files (its defines decide which `ifdef branches are active) |
classes/ |
shapes.sv |
A class hierarchy with a virtual method and its overrides |
uvm/ |
my_if.sv, my_pkg.sv, tb_top.sv |
A minimal UVM testbench: interface with a clocking block and modport, sequence item, sequence, driver, agent, environment and top module |
The UVM library itself is not included, so names that come from uvm_pkg (for example uvm_driver or
uvm_config_db) cannot be navigated to. Everything declared in the sample project can.