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Sample project

Every feature page has a Try it section: short steps with the result you should see. They all use this one sample project, so you can follow the guide without setting up your own code. It has a counter, a top level, a class hierarchy, a macro file and a small UVM testbench: everything the examples need. You can edit the files freely; each step that changes something says how to undo it, and you can start over by unzipping the download again.

  1. Download sample-project.zip and unzip it. Finder (double-click) and Windows Extract All… create a sample-project folder for you; on Linux run unzip sample-project.zip -d sample-project. Afterwards the folder sample-project must contain rtl, classes and uvm directly (the files are at the top level of the zip).
  2. In the IDE (IntelliJ IDEA, CLion, PyCharm or another IntelliJ-based IDE with the plugin installed), choose File | Open… (on the welcome screen, Open) and select that sample-project folder. If the IDE asks whether to trust the project, choose Trust Project. If it asks about a new window, either answer works; keep one window for the whole guide. Ignore any prompt to set up an SDK or a build system: the guide does not need one.
  3. Wait until indexing has finished. Indexing is the IDE scanning your files so that it can look names up; its progress bar is at the bottom right of the window, and it is gone when indexing is done.

You should see the folders rtl, classes and uvm in the Project tool window (the file tree on the left; if it is hidden, press ⌘1 on macOS, Alt+1 on Windows/Linux). Open rtl/counter.sv: keywords such as module and always_ff have one color, names such as clk and MAX others (the exact colors depend on your theme).

rtl/counter.sv in the SystemVerilog Studio Dark color scheme: keywords, types, numbers and names have different colors

Check that it works beyond colors: ⌘-click (macOS) / Ctrl-click (Windows/Linux) the first word counter in rtl/top.sv, in the line counter #(.MAX(20)) u_counter; rtl/counter.sv opens at module counter (if counter.sv is already open in a tab, close that tab first, so that you see it open again). If nothing is colored or the click does nothing, see If it doesn’t work.

Pages that use each file are linked in the last column.

Folder Files What it is Used by
rtl/ counter_pkg.sv, counter.sv, top.sv A counter module with its package (an enum and a function), and a top level that instantiates it Go to Declaration, Find Usages, Rename, Undeclared names
rtl/ defines.svh The macros LANES and COUNTER Macros
rtl/ legacy_reg.v, edge_pair.v An older Verilog-95 style module; two edge detectors with Emacs verilog-mode AUTO comments verilog-mode AUTOs
classes/ shapes.sv Classes with a method and its overrides Unknown members, Rename
uvm/ my_if.sv, my_pkg.sv, tb_top.sv A small testbench for the counter in UVM (the standard SystemVerilog verification library) UVM
(project root) sim.f, README.md sim.f is a compile file: the list of source files and defines you would give a simulator Conditional compilation

The plugin reads sim.f by itself, because it is the project’s only .f file (the default setting; see Conditional compilation). It lists counter_pkg.sv, counter.sv and top.sv and defines no macros, so the `ifdef GATE_LEVEL branch in top.sv is inactive and its `else branch is active. Open rtl/top.sv to see it: the initial $sdf_annotate(…) line inside the `ifdef is greyed out (Conditional compilation). The UVM library itself is not included, so UVM names such as uvm_driver or uvm_config_db (they come from the package uvm_pkg) have no declaration to jump to: ⌘-click (Ctrl-click) on one finds nothing. That is expected, not a fault of the plugin; see Known limitations. Everything declared in the sample project can be navigated.

You see Likely cause What to do
The tree shows a folder inside a folder, with no rtl at the top You opened the parent folder Open the inner sample-project folder
Navigation does nothing right after opening Indexing is not finished (a progress bar at the bottom of the window) Wait for it to finish
The IDE shows a banner about a project that is not trusted The project was opened in restricted mode Choose Trust Project
The files look edited from an earlier step A step was not undone Close the project (File | Close Project), unzip the download into a new folder and open that folder
Colored, but ⌘/Ctrl-click does nothing, and indexing has finished The click was on u_counter or another word Click the first word counter; see Known limitations
rtl/counter.sv is plain text The plugin is not installed or is disabled Settings (⌘, on macOS; File | Settings… on Windows/Linux), then Plugins | Installed; see Installation

Next: your first project, or start with any page’s Try it.