New file from a template

File | New | SystemVerilog File (or New in the context menu of a directory) asks for a name and a kind and creates the file with its skeleton, named after the file:

Kind	File	Contents
Module	name.sv	module name (); … endmodule : name
Interface	name.sv	interface name (); … endinterface : name
Package	name.sv	package name; … endpackage : name
Class	name.sv	a class with a constructor, inside an include guard
Program	name.sv	program name (); … endprogram : name
Header (.svh)	name.svh	an include guard (`ifndef NAME_SVH) around a class
Verilog-2001 module (.v)	name.v	module name (); … endmodule (no end label)

The name must be a SystemVerilog identifier that is not a keyword (fifo_ctrl, not fifo-ctrl or module). The templates can be changed in Settings | Editor | File and Code Templates; every file starts with the SystemVerilog File Header include.

Try it

1. In the sample project, right-click the rtl directory and choose New | SystemVerilog File.
2. Type fifo-ctrl: the dialog reports that it is not a SystemVerilog identifier. Change it to fifo_ctrl, choose Module and press Enter.
3. rtl/fifo_ctrl.sv opens with module fifo_ctrl (); and endmodule : fifo_ctrl.