New file from a template

A new file made from a template starts with the right skeleton: the unit and its end label (the : fifo_ctrl after endmodule: module fifo_ctrl (); … endmodule : fifo_ctrl), the file header (author, copyright and creation date), and for classes and headers an include guard (a pair of `ifndef / `define lines that stops a file from being read twice). You do not type or misspell that boilerplate. Choose File | New | SystemVerilog File, or right-click a directory in the Project tool window and choose New | SystemVerilog File. The dialog asks for a name and a kind.

Try it

The steps use the sample project, open in the IDE.

1. Right-click the rtl directory in the Project tool window (the file tree on the left) and choose New | SystemVerilog File.

2. A dialog opens with a field for the name and a list of kinds below it. Type fifo-ctrl: the dialog shows the message 'fifo-ctrl' is not a SystemVerilog identifier (a hyphen is not allowed in a name; it would be a minus).

3. Change the name to fifo_ctrl, select Module in the list and press Enter.

4. rtl/fifo_ctrl.sv is created in the rtl folder and opens. It reads (the date, time and user name are yours):

   // -------------------------------------------------------------------
   // @author your_user_name
   // @copyright (C) 2026, <COMPANY>
   //
   // Created : 2. Oct 2026 13:41
   //-------------------------------------------------------------------
   
   module fifo_ctrl ();
   
   endmodule : fifo_ctrl

5. To leave the sample project as it was, right-click fifo_ctrl.sv in the Project tool window and choose Delete and confirm.

If the menu entry or the dialog is missing, see If it doesn’t work.

Kinds

Kind	File	Contents
Module	name.sv	module name (); … endmodule : name
Interface	name.sv	interface name (); … endinterface : name
Package	name.sv	package name; … endpackage : name
Class	name.sv	a class with a constructor, inside an include guard (below)
Program	name.sv	program name (); … endprogram : name
Header (.svh)	name.svh	an include guard around a class
Verilog-2001 module (.v)	name.v	module name (); … endmodule (no end label: an end label is the : name after endmodule)

A class, or a header, is generated like this (for the name fifo_ctrl, after the file header):

`ifndef FIFO_CTRL_SVH
`define FIFO_CTRL_SVH

class fifo_ctrl;

  //class properties

  //constructor
  function new();
  endfunction

  //class methods

endclass : fifo_ctrl

`endif // FIFO_CTRL_SVH

The include guard name is the file name in capitals followed by _SVH (the Class kind uses the same template, so its guard also ends in _SVH although its file is .sv). Choose Header for a file that other files pull in with `include, Class for a file you compile directly.

Names and templates

The name must be a SystemVerilog identifier that is not a keyword: fifo_ctrl is accepted; fifo-ctrl is not an identifier, and module is a keyword (the dialog says 'module' is a SystemVerilog keyword). An empty name gets the message Enter a name.

The templates can be changed in Settings (⌘, on macOS / Ctrl+Alt+S on Windows/Linux) | Editor | File and Code Templates. Every file starts with the SystemVerilog File Header include (the author, the copyright with <COMPANY> as its default, and the creation date), which you edit under Includes on that page.

If it doesn’t work

You see	Likely cause	What to do
There is no SystemVerilog File entry under New	The plugin is not installed or is disabled	See Installation
Enter does nothing	No kind is selected in the list	Select a kind first
The dialog does not accept the name	It is not an identifier, or it is a keyword	Use letters, digits, _ and $, starting with a letter or _
The file is created in an unexpected folder	You started from another directory	Right-click the directory you want, then New

See also Troubleshooting.